1. Field of the Invention
The invention relates to a semiconductor wafer mode controlling assembly and, more particularly, to such an assembly in which modes of circuitry of dice (ICs) on the wafer are controlled through alternating signals applied to the dice through probe pads on the wafers. The invention also includes methods for constructing and operating such wafers the assembly.
2. State of the Art
Typically, finished integrated circuit chip assemblies include a die or dice attached to a lead frame and encapsulated with an encapsulant. Numerous expensive and time consuming steps are involved in producing such chip assemblies. These steps may include the following: (1) forming dice on a wafer substrate, (2) testing the dice, (3) cutting dice from the wafer, (4) connecting a die or dice to a lead frame, (5) encapsulating the die or dice, lead frame, connecting wires, and any auxiliary circuitry, (6) performing burn-in and providing other stresses to the dice, and (7) testing the assembly.
Defects in a finished chip assembly can prevent it from operating as intended. In spite of painstaking attention to detail, defects may be introduced at various levels of production. For example, manufacturing defects in the die may cause a failure. It has been found, however, that some defects are manifest immediately, while other defects are manifest only after the die has been operated for some period of time.
Reliability curves are used to express a hazard rate or instantaneous failure rate h(t) over time t, and often have a “bath tub” shape. The reliability curves for many, if not all, ICs are generally like that shown in FIG. 1. The reliability curve in FIG. 1 may be divided into three regions: (1) an infant mortality region, (2) a random failures region, and (3) a wearout region.
The infant mortality region begins at time t0, which occurs upon completion of the manufacturing process and initial electrical test. Some ICs, of course, fail the initial electrical test. Inherent manufacturing defects are generally expected in a small percentage of ICs, even though the ICs are functional at time t0. Because of these inherent manufacturing defects (that may be caused by contamination and/or process variability), these ICs have shorter lifetimes than the remaining population. Typically known as ICs suffering “infant mortalities,” while the ICs may constitute a small fraction of the total population, they are the largest contributor to early-life failure rates.
Once ICs subject to infant mortality failure rates have been removed from the IC population, the remaining ICs have a very low and stable field failure rate. The relatively flat, bottom portion of the bathtub curve, referred to as the random failure region, represents stable field-failure rates which occur after the IC failures due to infant mortalities have been removed and before IC wearout occurs.
Eventually, as wearout occurs, the failure rate of the ICs begins to increase rapidly. However, the average lifetime of an IC is not clearly understood, because most lab tests simulate only a few years of normal IC operation.
“Burn-in” refers to the process of accelerating failures that occur during the infant morality phase of component life in order to remove the inherently weaker ICs. The process has been regarded as critical for product reliability since the semiconductor industry began. There have been two basic types of burn-in. During the process known as “static” burn-in, temperatures are increased (or sometimes decreased) while only some of the pins on a test IC are biased. No data is written to the IC, nor is the IC exercised under stress during static burn-in. During “unmonitored dynamic” burn-in, temperatures are increased while the pins on the test IC are biased. The IC is cycled under stress, and data patterns are written to the IC but not read. Hence, there is no way of knowing whether the data written is retained by the cell.
In recent years, as memory systems have grown in complexity, the need for more and more reliable components has escalated. This need has been met in two ways. First, manufacturing process technology has reached a level of maturity and stability where inherent manufacturing defects, caused by contamination and process variation, have been reduced. As a result, latent failures have been significantly reduced, resulting in lower field failure rates. Secondly, more sophisticated methods of screening infant mortalities have been developed. As IC manufacturing practices have become more consistent, it has become clear that burn-in systems that simply provide stress stimuli in the form of high temperature and VCC (power) to the IC under test may be inadequate in two areas: (1) such burn-in systems cannot detect and screen infant mortality failure rates measured in small fractions of a percent, (2) such burn-in systems are unable to confirm random failure rates that are claimed to be significantly lower than 100 FITs (i.e., fewer than 100 failures per billion IC hours) at normal system operating conditions.
To address these issues, an “intelligent burn-in” approach can be utilized. The term “intelligent burn-in,” as used in this discussion, refers to the ability to combine functional, programmable testing with the traditional burn-in cycling of the IC under test in the same chamber. Advantages to this approach include:                (1) The ability to identify when a failure occurs and, thereby, compute infant morality rates as a function of burn-in time. As a result, an optimal burn-in time for each product family can be established.        (2) The ability to correlate burn-in failure rates with life test data typically obtained by IC manufacturers to determine the field failure rates of their products.        (3) The ability to incorporate into the burn-in process certain tests traditionally performed using automatic test equipment (ATE) systems, thereby reducing costs.        
Some ICs have internal test modes not accessible during normal operation. These test modes may be invoked on ATE by applying a high voltage to a single pin. The IC is then addressed in a manner so as to specify the operating mode of interest. Operating modes such as data compression, grounded substrate, and cell plate biasing can be enabled, thus allowing evaluation of IC sensitivities and help in isolating possible failure mechanisms.
The electrical characterization data gathered from these tests is used to identify which part of the circuit appears to be malfunctioning, the possible location(s) on the IC, and the probable type or nature of the defect. To facilitate discussion and reporting, failures are often classified according to their electrical characteristics, referred to as the failure mode. Typical classification of these modes includes the following: single cell defect, adjacent cell defect, row failure, column failure, address failure, open pin, supply leakage, pin leakage, standby current leakage, and entire array failure (all dead cells).
In anticipation that some ICs will have defects, many ICs are designed with redundancies. In such ICs, a defective section of the IC may be shut off and a redundant but properly operating section activated and used in place of the defective section. For example, typical integrated memory circuits include arrays of memory cells arranged in rows and columns. In many such integrated memory arrays, several redundant rows and columns are provided to be used as substitutes for defective rows or columns of memory. When a defective row or column is identified, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make substitution of the redundant row or column substantially transparent to a system employing the memory circuit, the memory circuit may include an address detection circuit. The address detection circuit monitors the row and column addresses and, when the address of a defective row or column is received, enables the redundant row or column instead.
One type of address detection circuit is a fuse-bank address detection circuit. Fuse-bank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address. The sense lines are programmed by blowing fuses in the sense lines in a pattern corresponding to the address of the defective row or column. Addresses are then detected by first applying a test voltage across the bank of sense lines. Then, bits of the address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of address bits, the sense lines all block current and the voltage across the bank remains high. Otherwise, at least one sense line conducts and the voltage falls. A high voltage thus indicates the programmed address has been detected. A low voltage indicates a different address has been applied.
Antifuses have been used in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be “blown” by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Various flash devices may be used.
Typically, ICs have numerous contacts that provide interfaces between the circuits within the die and the outside world. The contacts are used for bond pads to which bond wires are connected. The bond wires are also connected to the lead frame. The contacts (bond pads) may be used for various signals including those for addressing, data (DQ), VCC (power), VSS (ground), and control. However, physically, the contacts are extremely small or tiny. As such, it is impractical and expensive to provide direct connections between each of the contacts and probes used in, for example, testing, stressing, or repairing the IC. Probe pads that are much larger than die contacts have been placed on, for example, the edge of the wafer. However, the sheer volume of contacts limits the number of contacts to which probe pads may be practically connected.
If there is a defect in an IC, it is desirable to discover the defect as early as possible in the manufacturing process for a finished chip assembly. In that case, if it is determined that the defect cannot be repaired, the time and expense of completing a chip assembly will not be expended. Further, some repairs may be less expensive to repair at an earlier stage of production of the chip assembly.
Accordingly, it would be desirable to test, stress, and, if necessary, attempt to repair ICs while they are still on a wafer, rather than in a packaged chip assembly.
U.S. Pat. No. 5,504,369 to Dasse et al. describes an apparatus for performing wafer level testing of integrated circuit dice. Burn-in is described as being performed while the dice are still connected to the wafer. Conductors are connected between wafer contact pads and contacts (bonding pads) on dice. In a preferred embodiment, the conductors supply six voltage signals: power supply high voltage level signal, data signal, reset signal, clock signal, power supply memory programming voltage level signal, and ground voltage level signal. For the following reasons, connecting six conductors to each die has a considerable effect in terms of wafer real estate and/or processing steps. There are a large number of dice on the wafer. Current requirements dictate using numerous wafer contact pads and conductors to supply signals to the dice. Included extra conductors for redundancies increase the number by at least a factor of two. Further, the conductors are positioned on top of the dice and/or in the dicing lanes (streets or street area of the wafer). Placing all six conductors in the dicing lanes requires either stacking the conductors one on top of the other in a dicing lane, and/or widening the dicing lane (which may reduce the number of dice of the wafer). Placing several conductors over the dice requires additional processing steps. The processing steps may be further increased where conductors run both vertically and horizontally.
Accordingly, there is a need for an assembly in which a variety of signals may be supplied to dice in wafer form through a small number of contacts and conductive paths.